1. Field of the Invention
The present invention relates to a phase-locked loop and in particular to canceling or eliminating a parasitic current that leaks to the control voltage node of this phase-locked loop.
2. Description of the Related Art
Phase-locked loops (PLLs) are frequently used in communication systems to facilitate signal synchronization between a receiver and a transmitter. Specifically, a PLL can be used to synchronize a local oscillator in the receiver with a remote oscillator in the transmitter. This synchronization ensures that the local and remote oscillators have the same or a related frequency and, in some cases, phase.
FIG. 1A illustrates an exemplary phase-locked loop (PLL) 100. PLL 100 includes a phase detector 101, a charge pump 103, a filter 105, and a voltage-controlled oscillator (VCO) 106 (i.e. the local oscillator). Phase detector 101 detects the difference in frequency and phase between a reference signal R (which is extracted from, for example, a transmitted signal or a reference oscillator) and a feedback signal FB (which is an output of VCO 106). If there is a frequency/phase difference, then phase detector 101 generates output signals 102 whose amplitudes are related to that difference (called error signals).
In one embodiment, these error signals are “up” and “down” signals that charge pump 103 can use to source and sink current to and from filter 105 (e.g. a low-pass loop filter). For example, if the VCO frequency is too low, then phase detector 101 sets the “up” signal high, which triggers charge pump 103 to source current into filter 105, thereby increasing the voltage provided to VCO 106. On the other hand, if the VCO frequency is too high, then phase detector 101 sets the “down” signal high, which triggers charge pump 103 to sink current from filter 105, thereby reducing the voltage provided to VCO 106. The effect of the resulting control voltage Vc at control voltage node 104 is to adjust VCO 106 to the same frequency and phase as signal R.
The adjustment made in VCO 106 can be significantly distorted by parasitic current, which can be generated by certain transistors. In general, transistors of current sub-micron CMOS technologies tend to be leaky in their off (i.e. non-conducting) state. That is, a small (but undesirable) parasitic current flows from the drain to the source of a transistor when its gate-to-source voltage is zero (which defines an off state).
Certain transistors in charge pump 103, specifically those serving as switches to source or sink current, can cause significant performance issues if leakage current is present. For example, these sourcing/sinking transistors are ideally turned on for a tiny fraction of a reference period and are turned off (thereby ideally contributing zero current) for the rest of the period. Because these sourcing/sinking transistors actually generate leakage currents in their off state, certain capacitors (shown in FIG. 3A and described below) of filter 105 can be partially charged or discharged within the reference period.
This partial discharge causes an ideal control voltage Vc(ideal) to vary in a periodic manner, thereby resulting in an actual control voltage Vc(actual) shown by the sawtooth waveform in FIG. 1B. This variation in the control voltage Vc at control voltage node 104, in turn, can cause undesirable reference spurs in VCO 106. These reference spurs can detract from the desired signal purity expected of VCO 106.
Certain conditions, such as high temperature when the CMOS device threshold voltage is low, can increase transistor leakage in charge pump 103, thereby exacerbating the control voltage variation and associated spur generation. To minimize this variation in control voltage Vc, longer than minimum length transistors can be used for the sourcing/sinking transistors, thereby resulting in a higher threshold voltage for those transistors. Unfortunately, these larger transistors, although having less leakage, are slower than minimum length devices.
Therefore, a need arises for methods of and circuits for substantially reducing the parasitic current that leaks to the control voltage node of a PLL.